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Record 1,  Textual support,  English

Record number: 1, Textual support number: 1 CONT

(In the internal operation of a microprocessor,) an interrupt bit, which normally functions as an interrupt-enable, can be provided (within the flags register.) Whenever the interrupt bit is set, outside interrupts will be accepted. Whenever an interrupt bit is not set (0), external interrupts will be inhibited; they are said to be masked.  1, record 1, English, - interrupt%20bit

Record number: 1, Textual support number: 1 OBS

interrupt enable: an instruction that sets an interrupt-control flip-flop. This enables an armed interrupt so that data transfer can take place.  3, record 1, English, - interrupt%20bit

Record 1,  Textual support,  French

Record number: 1, Textual support number: 1 CONT

Le registre des indicateurs d'état peut (...) contenir un bit d'interruption, qui jouera le rôle de bit de validation des interruptions. Lorsqu'il se positionne à 1, les interruptions externes seront acceptées. Lorsqu'il se positionne à 0, elles seront inhibées (dans ce cas on dit qu'elles sont masquées).  1, record 1, French, - bit%20d%27interruption

Record 1,  Textual support,  Spanish